The present invention relates to the control by a plurality of co-processors in order to enhance an ability of arithmetic and/or logical operations of a host processor in a computer system, and more particularly to a designation control method of a co-processor identification code which is suitable in implementing an execution function of an instruction of the arithmetic and/or logical functions for the co-processor in the host processor with the advancement of integration technology of constituent elements of the processor.
In the past, the co-processor is externally connected to the host processor in order to compensate for a function which is not implemented on a host processor chip due to an integration limitation. For example, with the advance of display technology, a powerful floating point arithmetic operation function is required for coordinate transform of image displaying graphics. Further, since calculation may be independently done for each coordinate component, the use of two or more floating point arithmetic operation co-processors is advantageous. In a field of artificial intelligence processing which has recently been becoming an object of public attention, a presently available general purpose microprocessor is not sufficient to handle artificial intelligence processing because of speciality in processing. Accordingly, it is significant to externally connect an artificial intelligence processing co-processor to a host processor. In those instances, in order to handle and control two floating point arithmetic operation co-processors of the same type or a plurality of co-processors of different types such as one floating point operation co-processor and one artificial intelligence processing co-processor, co-processor identification codes are used so that an inherent number is assigned to each co-processor. For example, in the Motorola Inc. 32-bit microprocessor MC 68030 (detail of which is described in "MC 68030 Enhanced 32-bit Microprocessor User's Manual, 1987", Section 10. Co-processor Interface Description, distributed by Motorola Inc.), an instruction format shown in FIG. 2 is defined in order to externally connect the co-processors to the host processor, handle an instruction of operation for the co-processor and control the plurality of co-processors. Specific codes 1111 in bit positions 12-15 indicate that the instruction relates to the co-processor. When the host processor decodes the instruction, it can identify the instruction to be executed by the external co-processor by the specific code. Three bits at the bit positions 9-11 defines the co-processor identification code. They can designate up to eight co-processor numbers to identify co-processors of the same type or different types. The bit positions 6-8 are type identification code of the co-processor instruction. The bit positions 0-5 are a field which is defined depending on the type of instruction. In accordance with this instruction format of the arithmetic and/or logical operations for the co-processor, it is possible to design external co-processors having various functions such as floating point arithmetic operation co-processor and artificial intelligence processing co-processor and define specific content of the operating instructions in accordance with the respective functions. It is also possible to control a mixture of up to eight co-processors of the same type or different types.